Digital data transmission can be done either in parallel mode, serial mode, or a combination of the two. Parallel mode is the simplest to implement but it demands the most interconnect lines, which requires more space and complex routing, and often more power. Serial transmission requires only a single data line which implies less space and simplified routing, and it usually comes with a power savings. However, serial data transmission does require more speed per data line and can be much more complex to implement than parallel transmission. Analog to digital converters (ADCs) traditionally provide high speed parallel output to a receiver, embodied in e.g., FPGA, or ASIC. An N bit ADC has N lines or pins (2 N pins for a differential system) connecting it to the FPGA. For M converters there will be M×N (or M×2 N) pins. The greater the number, M, of ADCs and the greater the ADC resolution, N, the greater the number of pins. Higher output pin numbers makes routing to the receiver more complex. Power requirements can be high due to the number of output drivers necessary to drive the parallel output pins. One (or two) more pin(s) is required for the output data clock. In the parallel arrangement a twelve bit (N=12) ADC can reach sampling rates of several hundred Mbps corresponding to like bit rates at the FPGA. In another approach serial output is employed. There, instead of each bit of resolution of the ADC having its own output pin, all of the output bits of the ADC are streamed over a serial line or channel. This requires a much higher data rate. For example, an N bit ADC would parallel transfer all N bits in a single unit of time, while in a serial transfer all bits would have to be transferred in the single unit of time so each bit would have only 1/N th of the transfer time. Typically, in this approach, a number of ADCs 4, 8, 128 or more each have their own serial channel. Here another clock pin is needed to provide a frame clock in addition to the output data clock. The frame clock is used to distinguish each sample serially transferred. Here, too, the data channels can be skewed relative to each other and with respect to the output data clock. And it is cumbersome to make the clock edges adjustable so they can be properly aligned in unambiguous regions of the data in all channels. Here a sampling rate at 65 Mbps with 12 bit (N=12) ADCs results in a data rate at the FPGA of 780 Mbps. A specification of the JEDEC Solid State Technology Association for a Data Converter Serial Interface (JESD204) serializes each analog to digital conversion or sample and eliminates the clock pin or pins by using the embedded clock in the serialized data. But this approach also requires a feedback loop from receiver to transmitter to confirm a handshake protocol and then release the data for transmission. This approach uses an 8B/10B encoding scheme where every eight bits are accompanied by two more bits which are used for maintaining electrical balance and for error checking. This results in a maximum ideal efficiency of only 80%. Further, the error checking is not sufficiently robust to correct the errors and does not detect the errors in real time.